代码搜索:FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

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www.eeworm.com/read/194228/5136861

entries

/flash.c/1.1.1.1/Thu Nov 2 14:15:01 2006// /fpga.c/1.1.1.1/Thu Nov 2 14:15:01 2006// /pci.c/1.1.1.1/Thu Nov 2 14:15:01 2006// D
www.eeworm.com/read/190958/5170137

xco program.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\vhdl\l
www.eeworm.com/read/190958/5170266

xco program.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\vhdl\l
www.eeworm.com/read/277636/4153560

h vpe_m.h

#ifndef __VPE_M_H #define __VPE_M_H #include "portab.h" #define VPE 0x90180000 #ifdef FPGA #define mVpe_PASS() \ { \ printf("VPE pass\n"); \ } #ifdef ERROR_CONCEALMENT
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entries

/flash.c/1.1.1.1/Wed Dec 6 00:22:11 2006// /fpga.c/1.1.1.1/Wed Dec 6 00:22:11 2006// /pci.c/1.1.1.1/Wed Dec 6 00:22:11 2006// D
www.eeworm.com/read/366431/2890438

vhd addn.vhd

-- n-bit Adder using the Generate Statement -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY addn IS GENERIC(n : POSITIVE := 3); -
www.eeworm.com/read/366431/2890612

vhd moore1.vhd

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
www.eeworm.com/read/366431/2890651

vhd moore2.vhd

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
www.eeworm.com/read/471480/6894544

rpt speak.rpt

Project Information d:\fpga\cpld\speak\speak.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 11/20/2007 15:28:08 Copyright (C) 1988-2002 Al
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html readme.html

FPGA时钟讲解   更多资料请访问: http://www.xinworks.com ================