代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/149929/12330995
vhd addn.vhd
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); -
www.eeworm.com/read/149929/12331978
vhd moore1.vhd
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/149929/12332200
vhd moore2.vhd
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/149607/12362981
txt moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/149607/12363004
txt moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/227189/14437597
vhd 简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
www.eeworm.com/read/227189/14437633
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/227189/14437650
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/17771/760003
rpt speak.rpt
Project Information d:\fpga\cpld\speak\speak.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/20/2007 15:28:08
Copyright (C) 1988-2002 Al
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vhd ps2.vhd
-- The FPGA-evb-S2 Xilinx Spartan-II evaluation board example
--
-- This example reads scan codes from a PS/2 keyboard and
-- displays them on LEDs.
--
-- (C)2001 Jan Pech, j.pech@sh.cvut.cz