代码搜索:FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

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vhd decod.vhd

-- Progetto Elettronica 2 FPGA (2007) - Marco Mucchino & Giovanni Schiavon -- Decoder per circuito con 4 led a 7 segmenti library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use
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rpt speaker.rpt

Project Information d:\fpga\sample\speaker\speaker.rpt MAX+plus II Compiler Report File Version 10.0 9/14/2000 Compiled: 12/16/2003 11:48:41 Copyright (C) 1988-2000 Alt
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rpt spkctrl.rpt

Project Information d:\fpga\sample\speaker\spkctrl.rpt MAX+plus II Compiler Report File Version 10.0 9/14/2000 Compiled: 12/16/2003 11:57:23 Copyright (C) 1988-2000 Alt
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txt moor1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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txt moor2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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txt 简单的12位寄存器.txt

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
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txt 莫爾形狀態機2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
www.eeworm.com/read/345690/11795206

txt 莫爾形狀態機1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst: