代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/198238/7946528
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/197597/7984736
vhd 简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
www.eeworm.com/read/197597/7984813
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/197597/7984832
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/145313/12736117
vhd 简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
www.eeworm.com/read/145313/12736180
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/145313/12736207
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/246188/12752213
+=
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
www.eeworm.com/read/246188/12752227
-
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/246188/12752231
-
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst: