代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/291453/8417615

txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
·
www.eeworm.com/read/390924/8433397

txt 莫爾形狀態機2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
·
www.eeworm.com/read/390924/8433426

txt 莫爾形狀態機1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
·
www.eeworm.com/read/433021/8552016

vhd 莫尔型状态机.vhd

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
·
www.eeworm.com/read/433021/8552027

vhd 简单的12位寄存器.vhd

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
·
www.eeworm.com/read/168700/9901584

timesim_vhw t_compact.timesim_vhw

-- D:\FPGA\仿真\DIVIDER_定点除法器 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Thu Jul 13 10:54:53 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test
·
www.eeworm.com/read/168700/9901715

timesim_vhw t_divider.timesim_vhw

-- D:\FPGA\仿真\DIVIDER_定点除法器 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Thu Jul 13 10:58:04 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test
·
www.eeworm.com/read/168700/9901719

vhw t_divider.vhw

-- D:\FPGA\仿真\DIVIDER_定点除法器 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Thu Jul 13 10:59:57 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test
·
www.eeworm.com/read/164962/10080397

txt moor1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
·
www.eeworm.com/read/164962/10080408

txt moor2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
·