代码搜索:FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
www.eeworm.com/read/133091/6956290

c~ main.c~

#include #include "Omap30.h" #include "Omap30_armwdg.h" #include "..\header\armperipherals.h" #include "..\header\FPGA_peripherals.h" #include "swi.h" //int SetupGPIOHandler(unsigned
www.eeworm.com/read/133091/6956357

c main.c

#include #include "Omap30.h" #include "Omap30_armwdg.h" #include "..\header\armperipherals.h" #include "..\header\FPGA_peripherals.h" #include "swi.h" //int SetupGPIOHandler(unsigned
www.eeworm.com/read/448593/7529104

txt state_moor_mealy.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
www.eeworm.com/read/448593/7529105

txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
www.eeworm.com/read/443859/7621617

v generic_spram.v

`include "timescale.v" //`define VENDOR_XILINX //`define VENDOR_ALTERA `define VENDOR_FPGA module generic_spram( // Generic synchronous single-port RAM interface clk, rst, ce, we, oe, ad
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txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
www.eeworm.com/read/199789/7822624

txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
www.eeworm.com/read/398865/7914355

v generic_spram.v

`include "timescale.v" //`define VENDOR_XILINX //`define VENDOR_ALTERA `define VENDOR_FPGA module generic_spram( // Generic synchronous single-port RAM interface clk, rst, ce, we, oe, ad
www.eeworm.com/read/198238/7946367

txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
www.eeworm.com/read/198238/7946473

txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in