代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
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txt 帶莫爾_米勒輸出的狀態機.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
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txt 米勒形狀態機.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/387421/8685004
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
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h xlxram.h
/*
Simulation model of Xilinx FPGA BlockRAM memory
2002 A.S.Slusarczyk@tue.nl
*/
#ifndef XLXRAM_H_INCLUDED
#define XLXRAM_H_INCLUDED
#include
#include "mips.h"
#ifndef VERILOG
#inc
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v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
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vhw countest.vhw
-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 13:02:02 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Wa
www.eeworm.com/read/169299/9868127
vhw topwave.vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 11 13:47:18 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9868162
timesim_vhw topwave.timesim_vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Mon Apr 10 09:01:43 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9868180
timesim_vhw testwave.timesim_vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Apr 06 15:41:45 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben