代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/199789/7822606
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/198238/7946423
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/298088/7975006
txt pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
www.eeworm.com/read/145313/12736147
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/246188/12752085
-
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/145129/12752296
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/145059/12754599
txt 双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
www.eeworm.com/read/329969/12923069
tcl getpcmdata.tcl
########## Tcl recorder starts at 06/17/08 14:52:44 ##########
set version "7.0"
set proj_dir "D:/CPLD/FPGA"
cd $proj_dir
# Get directory paths
set pver $version
regsub -all {\.} $pver {_}
www.eeworm.com/read/140988/13048891
txt pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
www.eeworm.com/read/139685/13139850
txt bidir.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi