代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/21656/838573
txt status report.txt
Output: VHDL File
Type : VHDL
From : Project [FPGA_Project1.PrjFpg]
Generated File[Sheet1.VHD]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 16:52:21 On 20
www.eeworm.com/read/38966/1119182
txt status report.txt
Output: VHDL File
Type : VHDL
From : Project [FPGA_Project1.PrjFpg]
Generated File[CPU.VHD]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 16:07:45 On 2010-
www.eeworm.com/read/38966/1119197
txt status report.txt
Output: VHDL File
Type : VHDL
From : Project [FPGA_Project1.PrjFpg]
Generated File[Sheet1.VHD]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 17:30:38 On 20
www.eeworm.com/read/38966/1119210
txt status report.txt
Output: VHDL File
Type : VHDL
From : Project [FPGA_Project1.PrjFpg]
Generated File[Sheet1.VHD]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 16:52:21 On 20
www.eeworm.com/read/477919/1356660
lds u-boot.lds
/* Linker script for Gaisler Research AB's Template design
* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
*
* (C) Copyright 2008
* Daniel Hellstrom, Gaisler Research, daniel@
www.eeworm.com/read/440499/1796161
lds u-boot.lds
/* Linker script for Gaisler Research AB's Template design
* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
*
* (C) Copyright 2008
* Daniel Hellstrom, Gaisler Research, daniel@
www.eeworm.com/read/414420/2150321
lds u-boot.lds
/* Linker script for Gaisler Research AB's Template design
* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
*
* (C) Copyright 2008
* Daniel Hellstrom, Gaisler Research, daniel@
www.eeworm.com/read/412040/2177453
prd armexio.prd
#-- Synplicity, Inc.
#-- Version 7.3
#-- Project file E:\Exp22_1\FPGA\armExIO.prd
#-- Written on Thu Nov 20 16:55:42 2003
#
### Watch Implementation type ###
#
watch_impl -active
#
#
www.eeworm.com/read/368758/2811319
lds u-boot.lds
/* Linker script for Gaisler Research AB's Template design
* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
*
* (C) Copyright 2008
* Daniel Hellstrom, Gaisler Research, daniel@
www.eeworm.com/read/367504/2841960
pl hextoh.pl
#!/usr/bin/perl -w
print "static const unsigned char fpga_data[] = {\n";
$count = 0;
while ((read STDIN, $byte, 2) && ! eof STDIN) {
print " 0x$byte,";
$count ++;
if (($count % 8) == 0) {