代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/493094/1169466
c platform.c
/*
* \brief Platform for TE0304
* \author Norman Feske
* \date 2009-02-24
*/
/* FPGA includes */
#include "xparameters.h"
#include "mb_interface.h"
/* local includes */
#include "platform.h"
www.eeworm.com/read/459651/1566528
java fastpga.java
/**
* FPGA.java
* @author Juan J. Durillo
* @version 1.0
*/
package jmetal.metaheuristics.fastPGA;
import jmetal.base.*;
import jmetal.base.operator.comparator.FPGAFitnessComparator;
import jmetal.u
www.eeworm.com/read/318084/3571698
transcript
# Reading F:/FPGA/Modeltech_6.1f/tcl/vsim/pref.tcl
# // ModelSim SE 6.1f May 12 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // TH
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transcript
# Reading F:/FPGA/Modeltech_6.1f/tcl/vsim/pref.tcl
# // ModelSim SE 6.1f May 12 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // TH
www.eeworm.com/read/315673/3616881
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fifo_fpga is
port(
WD : in vl_logic_vector(7 downto 0);
RD : out vl_logic_vector(15 downto 0);
www.eeworm.com/read/300337/3847576
java fastpga.java
/**
* FPGA.java
* @author Juan J. Durillo
* @version 1.0
*/
package jmetal.metaheuristics.fastPGA;
import jmetal.base.*;
import jmetal.base.operator.comparator.FPGAFitnessComparator;
import jmetal.u
www.eeworm.com/read/373367/2763070
sh radar_tb.sh
#!/bin/sh
iverilog \
-D SIMULATION \
-y ../lib/ \
-y ../../../../usrp/fpga/sdr_lib \
-y ../models/ \
radar_tb.v -o radar_tb && ./radar_tb > radar_tb.out
www.eeworm.com/read/357802/3012977
c i2c.c
#include "api.h"
#include "i2c.h"
//#ifdef CONFIG_FPGA
//--------------------------------------------------------------------------
static void vI2C_Delay(void)
{
INT8U i;
for(i=10;i>
www.eeworm.com/read/174396/6790007
src altera1.src
# Altera Max+plus, EMax, Quartus and FPGA license file
FEATURE altera_fpgaexpress alterad 3000.0 permanent uncounted 0 HOSTID=000000000000 ck=0
FEATURE altera_mainwin alterad 3000.0 permanent unco
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vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l