代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/486955/6521484
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/263314/11367856
txt cpu_system.txt
-- Structural description of a Microprocessor System
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY cpudemo IS
END cpudemo;
ARCHITECTUR
www.eeworm.com/read/401301/11559728
v statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
www.eeworm.com/read/157209/11730133
txt 条件赋值：使用列举类型.txt
-- Selected Signal Assignment with Enumeration Type
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LU
www.eeworm.com/read/157209/11730192
txt 简单的锁存器.txt
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/152488/12110110
tdf dynram.tdf
TITLE "DRAM Controller with Refresh (CAS before RAS) and DTACK Generation" ;
-- Version 1.1, 03.02.1998
-- Copyright Frank Rodler
-- You can download it from www.fpga.com.cn or www.pld.com.cn
PA
www.eeworm.com/read/254980/12110209
v statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
www.eeworm.com/read/149607/12363021
txt cpu_system.txt
-- Structural description of a Microprocessor System
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY cpudemo IS
END cpudemo;
ARCHITECTUR
www.eeworm.com/read/233751/14141233
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/231389/14237183
makefile_arm
# /drivers/fpga/Makefile
# 2007/5 minifans
all:
/usr/local/arm/3.4.1/bin/arm-linux-gcc -Wall -g userTest.c -o armTest
clean:
rm -rf userTest.o armTest