代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/39742/1135392

vhd stubi.vhd

-- Generated PORTMAP Stub File: Created by Capture FPGA Flow -- Matches PCB component pinout with simulation model -- Created Wednesday, May 13, 2009 08:10:07 中国标准时间
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www.eeworm.com/read/493094/1169454

c platform.c

/* * \brief Platform for Starter Kit 3A * \author Norman Feske * \date 2008-08-17 */ /* FPGA includes */ #include "xparameters.h" #include "mb_interface.h" /* local includes */ #include "plat
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www.eeworm.com/read/493094/1169460

c platform.c

/* * \brief Platform for ML405 * \author Norman Feske * \author Matthias Alles * \date 2008-08-17 */ /* FPGA includes */ #include "xparameters.h" #ifdef __MICROBLAZE__ #include "mb_interface.
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www.eeworm.com/read/493094/1169463

c platform.c

/* * \brief Platform for ML507 * \author Norman Feske * \author Matthias Alles * \date 2008-08-17 */ /* FPGA includes */ #include "xparameters.h" #ifdef __MICROBLAZE__ #include "mb_interface.
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www.eeworm.com/read/490583/1197350

lst netlist.lst

f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v\counter16_top.ngc 1140719485 OK
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www.eeworm.com/read/483857/1274609

xco ram_descramb.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03" SET speedgrade = -12 SET simulationfiles = B
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www.eeworm.com/read/231617/4713886

out anal.out

Loading db file 'D:/Synopsys/FPGA_Express/lib/libraries/syn/gtech.db' Reading in the Synopsys vhdl primitives. G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd:
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www.eeworm.com/read/332396/3398786

xco ram_descramb.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03" SET speedgrade = -12 SET simulationfiles = B
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www.eeworm.com/read/325655/3481287

lst netlist.lst

f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v\counter16_top.ngc 1140719485 OK
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www.eeworm.com/read/318858/3561826

lst netlist.lst

f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v\counter16_top.ngc 1140719485 OK
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