代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/16498/673315
xco ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
www.eeworm.com/read/16802/692233
vhd stubi.vhd
-- Generated PORTMAP Stub File: Created by Capture FPGA Flow
-- Matches PCB component pinout with simulation model
-- Created Wednesday, May 13, 2009 08:10:07 中国标准时间
www.eeworm.com/read/17546/737926
v z80ip_t.v
//
// FPGA PACMAN Z80 interface for Daniel Wallner's T80
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freew
www.eeworm.com/read/17578/739832
xco ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
www.eeworm.com/read/17608/742439
v led.v
// Light 8 LED
// Designed By Smokingfish @ www.51FPGA.com zhiyuh@163.com
module LED (LED);
output [13:0] LED;
assign LED=14'b11100110111001;//"CP"
endmodule
www.eeworm.com/read/17872/763779
xco ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
www.eeworm.com/read/18028/771202
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
www.eeworm.com/read/18163/778499
xco ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
www.eeworm.com/read/18598/796652
scc mssccprj.scc
[SCC]
SCC=This is a source code control file
[FPGA串行通讯.vbp]
SCC_Project_Name=this project is not under source code control
SCC_Aux_Path=
www.eeworm.com/read/22036/840776
vhd stubi.vhd
-- Generated PORTMAP Stub File: Created by Capture FPGA Flow
-- Matches PCB component pinout with simulation model
-- Created Wednesday, May 13, 2009 08:10:07 中国标准时间