代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/18466/790125

cmd_log top.cmd_log

xst -intstyle ise -ifn __projnav/top.xst -ofn top.syr ngdbuild -intstyle ise -dd f:\project\videosampledesign\programme\myusbsampletest\1\fpga\fpga/_ngo -uc ucf.ucf -p xc3s400-pq208-4 top.ngc top.ng
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www.eeworm.com/read/18479/790397

cmd_log top.cmd_log

xst -intstyle ise -ifn __projnav/top.xst -ofn top.syr ngdbuild -intstyle ise -dd f:\project\videosampledesign\programme\myusbsampletest\1\fpga\fpga/_ngo -uc ucf.ucf -p xc3s400-pq208-4 top.ngc top.ng
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www.eeworm.com/read/342142/3238570

entries

/README/1.2/Sun Nov 20 20:42:06 2005/-ko/D2006.05.22.16.00.00 /fpga.c/1.4/Thu Oct 13 14:47:31 2005/-ko/D2006.05.22.16.00.00 /fpga.h/1.1.1.1/Mon Jun 10 16:09:10 2002/-ko/D2006.05.22.16.00.00 D
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www.eeworm.com/read/325655/3481078

gfl lcm_flowplus.gfl

# XST flow : Creating project file rom_32x8.prj # xst flow : RunXST rom_32x8.prj __projnav/rom_32x8.xst ./xst # XST flow : Creating project file fpga_lcm.prj # xst flow : RunXST fpga_lcm.prj
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www.eeworm.com/read/318858/3561617

gfl lcm_flowplus.gfl

# XST flow : Creating project file rom_32x8.prj # xst flow : RunXST rom_32x8.prj __projnav/rom_32x8.xst ./xst # XST flow : Creating project file fpga_lcm.prj # xst flow : RunXST fpga_lcm.prj
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www.eeworm.com/read/440835/1787457

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc5vfx130t-
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www.eeworm.com/read/440818/1787497

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -w -intstyle ise -ol std -t 1 lvds_bist_top_map.ncd lvds_bist_to
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www.eeworm.com/read/440818/1787498

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\bitgen.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -f lvds_bist_top.ut lvds_bist_top.ncd s FormatS
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www.eeworm.com/read/440818/1787499

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc5vfx130t-ff173
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www.eeworm.com/read/427629/1969110

xrf ram_control_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v source_file = 1,
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