代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/353811/10416347

vhd 一个简单的状态机.vhd

-- MAX+plus II VHDL Example -- State Machine -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTIT
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www.eeworm.com/read/353811/10416476

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/353811/10416525

v 加法器源程序.v

// download from: www.pld.com.cn & www.fpga.com.cn module counter (count, clk, reset); output [7:0] count; input clk, reset; reg [7:0] count; parameter tpd_clk_to_count = 1; parameter
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www.eeworm.com/read/161016/10463574

txt 最高优先级编码器.txt

-- Highest Priority Encoder -- download from www.pld.com.cn & www.fpga.com.cn LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity priority is port(I : in bit_vector(7 downto 0); --input
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www.eeworm.com/read/161016/10463578

vhd 一个简单的状态机.vhd

-- MAX+plus II VHDL Example -- State Machine -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTIT
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www.eeworm.com/read/419980/10824827

c dev_c7200_iofpga.c

/* * Cisco 7200 (Predator) simulation platform. * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) * * Cisco C7200 (Predator) I/O FPGA: * - Simulates a NMC93C46 Serial EEPROM as CPU and Mi
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www.eeworm.com/read/417397/10991753

txt 一个简单的状态机.txt

-- MAX+plus II VHDL Example -- State Machine -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTIT
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www.eeworm.com/read/417397/10991771

txt 加法器：generate语句的应用.txt

-- n-bit Adder using the Generate Statement -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY addn IS GENERIC(n : POSITIVE := 3); --no.
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www.eeworm.com/read/417397/10991775

txt 条件赋值：使用when else语句.txt

-- Conditional Signal Assignment -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY condsig IS PORT ( input0, input1, sel : IN BI
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www.eeworm.com/read/417397/10991803

txt 带load、clr等功能的寄存器.txt

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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