代码搜索：EDA设计
找到约 10,000 项符合「EDA设计」的源代码
代码结果 10,000
www.eeworm.com/read/152702/12092226
tcl st_mult1.tcl
# Run with quartus_sh -t
set_global_assignment -section_id st_mult1 -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY
set_global_assignment -section_id eda_design_synthesis -name EDA_INPUT
www.eeworm.com/read/173752/9637399
psf control.psf
CLOCK(clk_ctrl_setting)
{
DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
INVERT_BASE_CLOCK = OFF;
DUTY_CYCLE = 49;
INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OF
www.eeworm.com/read/343462/11945890
jid sanjiaobo.jid
. SANJIAOBO sanjiaobo.abl d:\软件作业\eda\新建文件夹\sanjiaobo.abl
www.eeworm.com/read/272176/10967553
qsf time.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/379680/9188814
dat bookinfo.dat
[General Information]
书名=从算法设计到硬线逻辑的实现：复杂数字逻辑系统的Verilog HDL设计技术和方法
作者=
页数=292
SS号=0
出版日期=
www.eeworm.com/read/362541/9993401
qsf myled.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/429111/8818892
txt catalog.txt
part1.asp 第一部分 需求分析
part2.asp 第二部分 概要设计
part3.asp 第三部分 详细设计