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Driver 的代码
makefile.driver
#
# Copyright (c) 2007 Toilers Research Group - Colorado School of Mines
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitte
driver.bl0
#$ DATE Sun Apr 20 15:12:18 2003
#$ TOOL Edif2Blif version 8.2
#$ MODULE driver
#$ PINS 14 Efficiant Latch SH data1 data2 clk reset ccdin askdata dataclk addr0 addr1 addr2 addr3
#$ NODES 251 data
driver.tlg
Synthesizing work.driver.behavioral
Post processing for work.driver.behavioral
@W:"E:\TCD-1208\2003.4.20\driver.vhd":86:5:86:6|Feedback mux created for signal data2. Did you forget the set/reset ass
driver.edf
(edif DRIVER
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2002 3 19 22 48 48)
(author "Synplicity, Inc.")
(program
driver.srm
f "noname"; #file 0
f "d:\isptools\synpbase\lib\vhd\std.vhd"; #file 1
f "e:\tcd-1208\2003.4.20\driver.vhd"; #file 2
f "d:\isptools\synpbase\lib\vhd\std1164.vhd"; #file 3
f "d:\isptools\synpbase\li
driver.bl1
#$ TOOL ispDesignEXPERT 8.3.02.12
#$ DATE Sun Apr 20 15:12:18 2003
#$ MODULE driver
#$ PINS 14 Efficiant Latch SH data1 data2 clk reset ccdin askdata dataclk addr0 addr1 \
# addr2 addr3
#$ NODES
driver.vhd
library ieee;
use ieee.std_logic_1164.all; --引用库
USE ieee.std_logic_arith.ALL;
entity Driver is
port(Efficiant: out std_logic; --输出相素有效
Latch:out std_logic; --输出Latch
driver.jhd
MODULE Driver
driver.tcl
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file .\Driver.TCL
#-- Written on Sun Apr 20 15:12:11 2003
#-- begin a new section
project -new
#-- Device options
set_op
driver.exf
Section Cross Reference File
Design 'DRIVER' created Sun Apr 20 15:12:18 2003
Type New Name Original Name
// ------------------------------------------