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# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

Fri Jan 13 11:14:21 2006

--display_6_led.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity display_6_led is port(din0: in std_logic_vector(3 downto 0); din1: in std_logic_ve

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions,

Version 5.0 Build 148 04/26/2005 SJ Full Version 35 1901 OFF OFF OFF OFF OFF FV_OFF VRSM_ON VHSM_ON 0 # entity total # case_insensitive # source_file total.bdf 1137120530 23 # stora

[ProjectWorkspace] ptn_Child1=Frames ptn_Child2=ActionPoints [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1