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Analysis & Synthesis report for display Sun Aug 05 21:31:16 2007 Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; ------------------

Analysis & Synthesis Status : Successful - Sun Aug 05 21:31:16 2007 Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version Revision Name : display Top-level Entity Name : display Famil

|display clock => display[5]~reg0.CLK clock => display[4]~reg0.CLK clock => display[3]~reg0.CLK clock => display[2]~reg0.CLK clock => display[1]~reg0.CLK clock => display[0]~reg0.CLK clock => d

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY display IS PORT ( clock : IN STD_LOGIC; --clock is 4MHZ qin : IN STD_LOGIC_VECTOR(3 DOWNTO 0); displ

Timing Analyzer report for display Sun Aug 05 21:31:28 2007 Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; ---------------------

Flow report for display Sun Aug 05 21:31:28 2007 Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal

Simulator report for display Sun Aug 05 21:31:50 2007 Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. L

library ieee; use ieee.std_logic_1164.all; entity display is port (clk:in std_logic; shanshuo:in std_logic; num:in integer range 0 to 15; display:out std_logic_vector(0 to 6)); end; ar

%DISPLAY Display dataset information