代码搜索：Direction

找到约 10,000 项符合「Direction」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/457360/7327115

afl bb squeeze.afl

//------------------------------------------------------------------------------ // // Formula Name: BB squeeze // Author/Uploader: Vladimir Gaitanoff // E-mail: // Date/Time Ad
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www.eeworm.com/read/446056/7586217

txt eeprom.txt

============================================================================= List of generated methods in project: EEPROM THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. ======
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www.eeworm.com/read/446056/7586224

c byte1.c

/** ################################################################### ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. ** Filename : Byte1.C ** Project : EEPROM **
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www.eeworm.com/read/446056/7586233

h byte1.h

/** ################################################################### ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. ** Filename : Byte1.H ** Project : EEPROM **
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www.eeworm.com/read/439254/7713810

java wormlink.java

/* * * Copyright (c) 2007, Sun Microsystems, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the
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www.eeworm.com/read/399935/7821166

vhd counters.vhd

-- MAX+plus II VHDL Example -- Efficient Counter Inference -- Copyright (c) 1994 Altera Corporation ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear
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www.eeworm.com/read/199789/7822541

vhd 各种功能的计数器.vhd

-- MAX+plus II VHDL Example -- Efficient Counter Inference -- Copyright (c) 1994 Altera Corporation -- download from:www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all
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www.eeworm.com/read/433881/7905360

doc gifrsize.doc

GifRSize -------- Program to resize image size by integer factor, using bits deleting (scaling down) and bits duplication (scaling up). Usage: ------ Usage: GifRSize [-s Scale] [-x X
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www.eeworm.com/read/198238/7946261

vhd 各种功能的计数器.vhd

-- MAX+plus II VHDL Example -- Efficient Counter Inference -- Copyright (c) 1994 Altera Corporation -- download from:www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all
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www.eeworm.com/read/198238/7946507

txt 各种功能的计数器.txt

-- MAX+plus II VHDL Example -- Efficient Counter Inference -- Copyright (c) 1994 Altera Corporation -- download from:www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all
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