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glm.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
prev_cmp_glm.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
ex.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
prev_cmp_clock.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
clock.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
lpc2124.wsdt
adc/Debug
s3esk_startup.vhd
--
-- Reference design - Initial design for Spartan-3E Starter Kit when delivered.
--
-- Ken Chapman - Xilinx Ltd - January 2006
--
-- Constantly scroll the text 揝PARTAN-3E STARTER KIT" and "www.
aboutehlib3_0.txt
About EhLib 3
What's new in version 3.0
In TDBDateTimeEditEh
+ New values in TDateTimeKindEh type (property Kind).
TDateTimeKindEh = (dtkDateEh, dtkTimeEh, dtkDateTimeEh, dtkCu
readme.txt
DE2_Top
-------
This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output ports corresponding to
fulladder_4.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I