代码搜索结果

-z -q -c -m"./Debug/DEC6713_BOOT.map" -o"./Debug/DEC6713_BOOT.out" -stack400 -w -x -i"f:/dec6713/soft design/dec6713/csl/DEC6713_BOOT" -i"c:/ti/c6000/bios/lib" -i"c:/ti/c6000/rtdx/lib" -i"c:/ti/c6000/

-------------------------- DEC6713_BOOT.pjt - Debug -------------------------- "c:\ti\c6000\cgtools\bin\cl6x" -g -q -fr"f:/dec6713/soft design/dec6713/csl/DEC6713_BOOT/Debug" -fs"f:/dec6713/soft de

-z -q -c -m"./Debug/DEC6713_BOOT.map" -o"./Debug/DEC6713_BOOT.out" -stack400 -w -x -i"f:/dec6713/soft design/dec6713/csl/DEC6713_BOOT" -i"c:/ti/c6000/bios/lib" -i"c:/ti/c6000/rtdx/lib" -i"c:/ti/c6000/

------------------------- DEC6713_Timer.pjt - Debug ------------------------- "c:\ti\c6000\cgtools\bin\cl6x" -g -q -fr"F:/DEC6713/Soft Design/DEC6713/CSL/DEC6713_Timer/Debug" -i"./include" -d"CHIP_

------------------------- DEC6713_FLASH.pjt - Debug ------------------------- "c:\ti\c6000\cgtools\bin\cl6x" -g -q -fr"f:/dec6713/soft design/programme2.0/DEC6713_FLASH/Debug" -i"f:/dec6713/soft de

(ExpressProject "" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\2000-11.dsn" (Type "Schematic Design")) (BuildF

Release 7.1i Map H.38 Xilinx Mapping Report File for Design 'swepfre' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -ise d:\rfid\rfid_re\rfid_re.ise -intstyle ise -

(ExpressProject "" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\sch_mlb1a4_v1.1_20061230.dsn" (Type "Schematic Desig

fpga reference design Offer:QuickLogic PCI Arbiter: Files: \APPS\pci arbiter\pci_arb.exe PCI Master/Target Design: Files: \APPS\PCI\MASTER\*.* Top Level Design: TOP.SCH Simulation Test Fixtur

Sample Waveforms for 4x40pll.tdf Sample behavioral waveforms for design file 4x40pll.tdf The following waveforms show t