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parity.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:31:07 12/18/2008
-- Design Name:
-- Module Name: parity - B
bookinfo.txt
005Computer Data Structures
010Introduction to Data Structures
023Fundamentals of Data Structures
034The Design and Analysis of Computer Algorithms
050Introduction to Numerical Analysis
067Numeri
oemodm.txt
ODM ODM
ODM（即ORIGINAL <mark>DESIGN</mark> MANUFACTURER）意为“原始设计制造商”，是指一家公司根据另一家公司的规格来设计和生产一个产品。某制造商设计出一种产品后，在某些情况下可能会被另外一些品牌的制造商看中，要求配上后者的品牌名称来进行生产，又或者稍微修改一些设计(如按键位置)来生产。这样做的最大好处是其他厂商减少了自己研制的时间。例如，计算机公司如HP公司可能会 ...
exa060603.m
%----------------------------------------------------------------------------
% exa060603.m, for example 6.6.3;
% To design IIR Butteworth bandstop DF by analog-lowpass,
% -------------------------
exa060601.m
%-----------------------------------------------------------------------------
% exa060601_1.m , for example 6.6.1
% to test buttord,lp2Hp,bilinear and butter
% to design high-pass DF with s=2/Ts[
pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
i2c_sl~2.sty
[Normal]
synlibXRef=lc4k_vlg, Verilog.TASKLSVlog, 0, Yes
_vlog_std_v2001=lc4k_vlg, Verilog.TASKLSVlog, 0, True
[STRATEGY-LIST]
Normal=True, 1125078904
[TOUCHED-REPORT]
Design.bl2File=1125087229
video.pin
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and a
altpll0_waveforms.html
Sample Waveforms for altpll0.v
Sample behavioral waveforms for design file altpll0.v
The following waveforms show the b
lpm_rom0_waveforms.html
Sample Waveforms for lpm_rom0.v
Sample behavioral waveforms for design file lpm_rom0.v
The following waveforms show the