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JDF E // Created by ISE ver 1.0 PROJECT send DESIGN send Normal DEVKIT XC95108 PC84 DEVFAM xc9500 FLOW XST Verilog MODULE send.v MODSTYLE uart_send Normal [STRATEGY-LIST] Normal=True, 1038

[send] Generate Programming File=true Design Entry Utilities=false User Constraints=false Synthesize=false Fit=true Implement Design=false

[send] Generate Programming File=true Design Entry Utilities=false User Constraints=true

[receive] Generate Programming File=true Design Entry Utilities=false User Constraints=true

JDF E // Created by ISE ver 1.0 PROJECT receive DESIGN receive Normal DEVKIT XC95108 PC84 DEVFAM xc9500 FLOW XST Verilog MODULE receive.v MODSTYLE uart_rec Normal [STRATEGY-LIST] Normal=Tr

% % FIR filter design using Hamming window % ORD1=511; F=8000; N=128; x=(0:127)/256*F; % Nth order Lowpass f1=1200; Wn=f1/F*2; blp=fir1(ORD1,Wn); BLP=blp*32767; m=freqz(blp,1,N); plot(x

%Parameters for QFT contrl design clear all; %close all; %Controller k=9; p1=42.81; p2=743+669.3i; p3=743-669.3i; z1=1.1; z2=113.8; %Pre-filter pf1=2.8+2.857i; pf2=2.8-2.857i;

% G and F design for QFT clear all; close all; % Controller k=800; z=150; p=50000; G=tf(k*[1/z,1],[1/p,1]); [numG,denG]=tfdata(G,'v'); % Filter k=1; p=150; F=tf(k,[1/p,1]); [numF,denF

%Parameters for QFT contrl design clear all; close all; %Controller k=379; z1=42; p1=123.5+213.9i; p2=123.5-213.9i;

function cntstor % CNTSTOR Store controller matrix. (Utility Function) % CNTSTOR stores the present design within the IDE environment. % It is then retrieved using CNTRECL. % Aut