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executing a query at design time.htm
Executing a query at design time
supplying parameters at design time.htm
Supplying parameters at design time
decode_2.v
//
// Module: DECODE_2
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
decode_3.v
//
// Module: DECODE_3
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
decode_4.v
//
// Module: DECODE_4
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
decode_1.v
//
// Module: DECODE_1
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
parameters.v
//
// Module: parameters
// Design: CAM_Top
// Verilog code: Defines Parameters for CAM design
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2 - Option = Preserve Hierarchy
// En
yimaqi.syn
JDF B
// Created by Version 8.1
PROJECT Untitled
DESIGN yimaqi Normal
DEVKIT ispLSI1032E-100LJ84
ENTRY ABEL/Schematic
DOCUMENT yimaqi.ppn
MODULE yimaqi.sch
MODSTYLE yimaqi Normal
yimaqi.can
//Design File: yimaqi.lif
//Design TimeStamp: 1144671722 Mon Apr 10 20:22:02 2006
//megablock GLB Phy GLB Log index name pin type no list o
dcount_waveforms.html
Sample Waveforms for DCOUNT.vhd
Sample behavioral waveforms for design file DCOUNT.vhd
The following waveforms show the