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output_design.vhd

--output design --v0.1 library ieee; use ieee.std_logic_1164.all; entity output_design is port( sout0: in std_logic; sout1: in std_logic; sout2: in std_logic; sout3: in std_logic

output_design.hif

Version 6.0 Build 178 04/27/2006 SJ Full Version 39 2097 OFF OFF OFF OFF OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- -

output_design.pin

-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

design.jpx.local~

debug.NoTracingClasses.1[0]=23 com.borland.datastore.*1 1 -1 debug.NoTracingClasses.10[0]=7 javax.*1 1 -1 debug.NoTracingClasses.11[0]=5 sun.*1 1 -1 debug.NoTracingClasses.12[0]=23 com.borland

design.jpx.local

build.menu.1[0]=com.borland.jbuilder.build.ProjectBuilder$ProjectBuildAction;make build.menu.2[0]=com.borland.jbuilder.build.ProjectBuilder$ProjectBuildAction;rebuild debug.NoTracingClasses.1[0]=23