代码搜索结果

(ExpressProject "" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\amcc405ep1.1_release.dsn" (Type "Schematic Design"))

[music] Implement Design=true Synthesize=false

Release 5.2i - ngd2vhdl F.28 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. ngd2vhdl: Reading design music.nga ... WARNING:NetListWriters:431 - Design does not contain hierarchical blocks

#/bin/sh # machine-generated shell-script to build SOPC Builder design # 2004.54.24 sc-build-ii make -f build.mak

Release 6.3.03i Map G.38 Xilinx Mapping Report File for Design 'indicator' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2v40-fg256-5 -cm area -p

#include //预处理文件里面定义了特殊寄存器的名称如P1口定义为P1 void main(void) { //定义花样数据，数据存放在片内CODE区中 unsigned char code design[]={0xFF,0xFE,0xFD,0xFB,0xF7,0xEF,0xDF,0xBF,0x7F,

#include //预处理文件里面定义了特殊寄存器的名称如P1口定义为P1 void main(void) { //定义花样数据 const unsigned char design[32]={0xFF,0xFE,0xFD,0xFB,0xF7,0xEF,0xDF,0xBF,0x7F, 0x7F

%-------------------------------------------------------------------------- % example6_20; % to test buttord.m and butter.m; % to design a Butterworth Bandpass digital filter. % ------------------

Sample Waveforms for pll.tdf Sample behavioral waveforms for design file pll.tdf The following waveforms show the behav

cdlver completed successfully. Design: Finished: Mon Oct 15 14:15:25 2007 Total CPU Time: 00:00:12 Total Elapsed Time: 00:00:13