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Release 6.3i - netgen G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Reading design adder4.ngd ... Flattening design ... Flattening design completed. Specializing design ... S

Release 6.3i - netgen G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Reading design adder4.ngd ... Flattening design ... Flattening design completed. Specializing design ... S

# @(#)xpz.menu 1.1 6/18/91 ERL - Interactive filter design demo " Filter Design " shell xpz -g1 -Ifilters/xpz.feafilt filters/proto.filt

E:/my_design/PLD_design/01_transmitter/db/transmitter.sim.vwf 0 200000000000 815 200000000000 0 E:/my_design/PLD_design/01_transmitter/transmitter.vwf 0 200000000000 600 200000000000 0 transmitter.v

set QESS_ROOTDIR=c:\altera\71\quartus set QUARTUS_ROOTDIR=c:\altera\71\quartus cd D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import "C:\altera\71\ip\nco\lib\..\..\co

set QESS_ROOTDIR=c:\altera\71\quartus set QUARTUS_ROOTDIR=c:\altera\71\quartus cd D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import "C:\altera\71\ip\nco\lib\..\..\co

############################################################################ # Design Compiler Reference Methodology # Version: B-2008.09 (Oct. 3, 2008) # Copyright (C) 2007, 2008 Synopsys All rights

Release 6.3i - netgen G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Reading design count4.nga ... Flattening design ... Flattening design completed. Specializing design ... S

Release 6.3i - netgen G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Reading design sel4_1.nga ... Flattening design ... Flattening design completed. Specializing design ... S