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Design 的代码
counter design.hex
:10000000758905758C00758A00D28C858A900200EE
:010010000BE4
:00000001FF
counter design.opt
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm {
counter design.lnp
"Counter Design.obj"
TO "Counter Design"
counter design.asm
ORG 0
MOV TMOD,#00000101B ;置T0计数器方式1
MOV TH0,#0 ;置T0初值
MOV TL0,#0
SETB TR0 ;T0运行
LOOP: MOV P1,TL0 ;记录P1口脉冲个数
LJMP LOOP ;返回
END
counter design.plg
礦ision3 Build Log
Project:
E:\Program Files\Labcenter Electronics\Proteus 6 Demonstration(2)\43 Counter Design\Counter Design.uv2
Project File Date: 07/29/
counter design.lst
A51 MACRO ASSEMBLER COUNTER_DESIGN 07/29/2006 16:21:09 PAGE 1
MACRO ASSEMBLER A51 V8.00
OBJECT MODULE PLACED IN Counter Design.OBJ
ASS
counter design.asm
ORG 0
MOV TMOD,#00000101B ;置T0计数器方式1
MOV TH0,#0 ;置T0初值
MOV TL0,#0
SETB TR0 ;T0运行
LOOP: MOV P1,TL0 ;记录P1口脉冲个数
LJMP LOOP ;返回
END
read_design.inc
/* Set search path for verilog include files */
search_path = search_path + RTL_PATH + { GATE_PATH }
/* Read verilog files of the OR1200 IP core */
if (TOPLEVEL == "or1200_top") {
read -f verilog o
design1.opj
(ExpressProject "Design1"
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(NoModify)
(File ".\design1.dsn"
(Type "Schematic