代码搜索：Decode
找到约 10,000 项符合「Decode」的源代码
代码结果 10,000
www.eeworm.com/read/14659/400686
srm decode.srm
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\example-4-21\asyn_bad\write_reg.v"; #file 3
f "c:\prj\example-4-21\asyn_bad\top.v"; #file 4
www.eeworm.com/read/14659/400687
edn decode.edn
(edif top
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2006 3 9 2 5 15)
(author "Synplicity, Inc.")
(program "Synpl
www.eeworm.com/read/14659/400688
tlg decode.tlg
Selecting top level module top
@N:"C:\prj\Example-4-21\asyn_bad\decode.v":3:7:3:12|Synthesizing module decode
@W: CL118 :"C:\prj\Example-4-21\asyn_bad\decode.v":17:2:17:3|Latch generated from alwa
www.eeworm.com/read/14659/400689
fse decode.fse
www.eeworm.com/read/14659/400692
prf decode.prf
#
# Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R.
#
# Period Constraints
FREQUENCY PORT "CS_" 277.1 MHz;
# Output Constraints
# Input Constraints
BLOCK ASYNCPATHS;
www.eeworm.com/read/14659/400693
srs decode.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Thu M
www.eeworm.com/read/14659/400699
v decode.v
// decode circuit, combination logic
module decode (CS_, OE_, WR_, Addr, my_wr, my_rd, CS_reg1, CS_reg2, CS_reg3);
input CS_, OE_, WR_;
input [7:0] Addr;
output my_wr, my_rd;
www.eeworm.com/read/14659/400717
v decode.v
// decode circuit, combination logic
module decode (CS_, WR_, Addr, my_wr, my_rd, CS_reg1, CS_reg2, CS_reg3);
input CS_, WR_;
input [7:0] Addr;
output my_wr, my_rd;
output
www.eeworm.com/read/14659/400734
v decode.v
// decode circuit, combination logic
module decode (CS_, OE_, WR_, Addr, my_wr, my_rd, CS_reg1, CS_reg2, CS_reg3);
input CS_, OE_, WR_;
input [7:0] Addr;
output my_wr, my_rd;
www.eeworm.com/read/14659/401638
v decode.v
module decode (clock, reset, data_bus_in, addr_bus, data_bus_out);
input clock, reset;
input [7:0] data_bus_in;
input [7:0] addr_bus;
output [7:0] data_bus_out;
reg [7:0] data_bu