代码搜索：DR
找到约 10,000 项符合「DR」的源代码
代码结果 10,000
www.eeworm.com/read/304833/13785843
dr_
<mark>dr</mark>,医生
<mark>dr</mark>.sun yat-sen,孙逸仙博士，即孙中山
<mark>dr</mark>ab,n.黄灰色;单调adj.不鲜明的;淡褐色的
<mark>dr</mark>abness,n．乏味
<mark>dr</mark>af,即期汇票
<mark>dr</mark>aft plan,草案
<mark>dr</mark>aft,n.通风设备;草稿adj.v.起草;拉开
<mark>dr</mark>after,n.起草人;驮马
<mark>dr</mark>aftsman,n.起草者;立案者
<mark>dr</mark>aftsmanship,n.制图术
<mark>dr</mark>afty, ...
www.eeworm.com/read/192497/8378974
v dr.v
module dr(din, clk, rst, drload, dout);
input [7:0] din;
input clk, rst, drload;
output [7:0] dout;
reg [7:0]dout;
always @(posedge clk or posedge rst)
if(rst)
dout=0;
else if(drload)
dou
www.eeworm.com/read/290301/8490510
h dr.h
#if !defined(AFX_DR_H__CD6A87E5_5DBD_11D4_9FD5_5254ABDD2B16__INCLUDED_)
#define AFX_DR_H__CD6A87E5_5DBD_11D4_9FD5_5254ABDD2B16__INCLUDED_
#if _MSC_VER > 1000
#pragma once
#endif // _MSC_VER > 10
www.eeworm.com/read/290301/8490543
cpp dr.cpp
// DR.cpp : implementation file
//
#include "stdafx.h"
#include "bxt.h"
#include "DR.h"
#ifdef _DEBUG
#define new DEBUG_NEW
#undef THIS_FILE
static char THIS_FILE[] = __FILE__;
#endif
www.eeworm.com/read/290298/8490940
h dr.h
#if !defined(AFX_DR_H__CD6A87E5_5DBD_11D4_9FD5_5254ABDD2B16__INCLUDED_)
#define AFX_DR_H__CD6A87E5_5DBD_11D4_9FD5_5254ABDD2B16__INCLUDED_
#if _MSC_VER > 1000
#pragma once
#endif // _MSC_VER > 10
www.eeworm.com/read/290298/8490994
cpp dr.cpp
// DR.cpp : implementation file
//
#include "stdafx.h"
#include "bxt.h"
#include "DR.h"
#ifdef _DEBUG
#define new DEBUG_NEW
#undef THIS_FILE
static char THIS_FILE[] = __FILE__;
#endif
www.eeworm.com/read/289204/8568608
dr lk.dr
;*
;* $Id: lk.dr,v 1.15 2007/10/08 08:15:04 sunny Exp $
;*
; [Sample of Link Directive File]
; *************************************************************
; Link Directive File is created by us
www.eeworm.com/read/288533/8624270
class dr.class
www.eeworm.com/read/287546/8682982
v dr.v
module dr(din, clk, rst, drload, dout);
input [7:0] din;
input clk, rst, drload;
output [7:0] dout;
reg [7:0]dout;
always @(posedge clk or posedge rst)
if(rst)
dout=0;
else if(drload)
dou
www.eeworm.com/read/287546/8683038
v dr.v
module dr(din, clk,rst, drload, dout);
input[7:0]din;
input clk,rst, drload;
output[7:0]dout;
reg[7:0] dout;
always@(posedge clk or negedge rst)
if(!rst)
dout