代码搜索：DPA
找到约 133 项符合「DPA」的源代码
代码结果 133
www.eeworm.com/read/338256/3319239
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/338256/3319330
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/323894/3507355
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/278121/4147750
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/427629/1968963
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/427629/1969069
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/427629/1969209
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/427629/1969345
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/386605/2570026
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in
www.eeworm.com/read/381853/2640160
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_in