代码搜索：CycloneII
找到约 4,731 项符合「CycloneII」的源代码
代码结果 4,731
www.eeworm.com/read/340417/12161327
hif dispdecoder.hif
Version 4.2 Build 157 12/07/2004 SJ Full Version
29
1857
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
www.eeworm.com/read/147571/12545722
hif sci.hif
Version 4.2 Build 157 12/07/2004 SJ Full Version
35
1857
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
www.eeworm.com/read/236691/14002141
hif hdb3decoder.hif
Version 4.2 Build 157 12/07/2004 SJ Full Version
32
1559
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
www.eeworm.com/read/492760/1171427
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cycloneii_routing_
www.eeworm.com/read/492760/1171448
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_lcell_ff is
generic(
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff"
);
por
www.eeworm.com/read/492760/1171462
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end cycloneii_and1;
www.eeworm.com/read/466574/1510303
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cycloneii_routing_
www.eeworm.com/read/466574/1510311
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_lcell_ff is
generic(
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff"
);
por
www.eeworm.com/read/466574/1510316
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end cycloneii_and1;
www.eeworm.com/read/278121/4147694
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cycloneii_routing_