代码搜索：CycloneII
找到约 4,731 项符合「CycloneII」的源代码
代码结果 4,731
www.eeworm.com/read/278121/4147741
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_and16 is
port(
Y : out vl_logic_vector(15 downto 0);
IN1 : in vl_logic_vector(15 downto
www.eeworm.com/read/351808/3098764
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_clk_delay_ctrl is
generic(
behavioral_sim_delay: integer := 0;
delay_chain : string := "54";
delay_chain_mo
www.eeworm.com/read/351808/3098789
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_and16 is
port(
Y : out vl_logic_vector(15 downto 0);
IN1 : in vl_logic_vector(15 downto
www.eeworm.com/read/17853/762387
ptf class.ptf
CLASS freedev_cycloneII_50
{
BOARD_DEFAULTS
{
JTAG_device_index = "1";
REFDES U5
{
base = "0x08000000";
}
REFDES U59
{
base = "0x00060000";
www.eeworm.com/read/492760/1171434
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_b5mux21 is
port(
MO : out vl_logic_vector(4 downto 0);
A : in vl_logic_vector(4 downto
www.eeworm.com/read/492760/1171442
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_ram_block is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
www.eeworm.com/read/492760/1171478
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_b17mux21 is
port(
MO : out vl_logic_vector(16 downto 0);
A : in vl_logic_vector(16 dow
www.eeworm.com/read/466574/1510305
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_b5mux21 is
port(
MO : out vl_logic_vector(4 downto 0);
A : in vl_logic_vector(4 downto
www.eeworm.com/read/466574/1510307
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_ram_block is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
www.eeworm.com/read/466574/1510320
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_b17mux21 is
port(
MO : out vl_logic_vector(16 downto 0);
A : in vl_logic_vector(16 dow