代码搜索：CycloneII
找到约 4,731 项符合「CycloneII」的源代码
代码结果 4,731
www.eeworm.com/read/278121/4147714
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_io is
generic(
operation_mode : string := "input";
open_drain_output: string := "false";
bus_hold : st
www.eeworm.com/read/278121/4147718
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_clkctrl is
generic(
clock_type : string := "auto";
ena_register_mode: string := "falling edge";
lpm_type
www.eeworm.com/read/278121/4147728
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string
www.eeworm.com/read/351808/3098751
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_mac_out is
generic(
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : strin
www.eeworm.com/read/351808/3098754
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_lcell_comb is
generic(
lut_mask : integer := 65535;
sum_lutc_input : string := "datac";
lpm_type
www.eeworm.com/read/351808/3098758
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_out
www.eeworm.com/read/351808/3098777
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_io is
generic(
operation_mode : string := "input";
open_drain_output: string := "false";
bus_hold : st
www.eeworm.com/read/351808/3098779
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_clkctrl is
generic(
clock_type : string := "auto";
ena_register_mode: string := "falling edge";
lpm_type
www.eeworm.com/read/351808/3098784
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string
www.eeworm.com/read/492760/1171444
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_bmux21 is
port(
MO : out vl_logic_vector(15 downto 0);
A : in vl_logic_vector(15 downt