代码搜索：CycloneII
找到约 4,731 项符合「CycloneII」的源代码
代码结果 4,731
www.eeworm.com/read/466574/1510308
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_io is
generic(
operation_mode : string := "input";
open_drain_output: string := "false";
bus_hold : st
www.eeworm.com/read/466574/1510310
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_clkctrl is
generic(
clock_type : string := "auto";
ena_register_mode: string := "falling edge";
lpm_type
www.eeworm.com/read/466574/1510315
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string
www.eeworm.com/read/349457/3144647
ptf de2_board.ptf
SYSTEM DE2_Board
{
System_Wizard_Version = "5.10";
System_Wizard_Build = "176";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONEII";
clock_freq = "50000000";
g
www.eeworm.com/read/349457/3144682
00 de2_board.ptf.5.00
SYSTEM DE2_Board
{
System_Wizard_Version = "5.00";
System_Wizard_Build = "168";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONEII";
clock_freq = "50000000";
g
www.eeworm.com/read/349168/3146920
ptf de2_board.ptf
SYSTEM DE2_Board
{
System_Wizard_Version = "5.10";
System_Wizard_Build = "176";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONEII";
clock_freq = "50000000";
g
www.eeworm.com/read/349168/3146955
00 de2_board.ptf.5.00
SYSTEM DE2_Board
{
System_Wizard_Version = "5.00";
System_Wizard_Build = "168";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONEII";
clock_freq = "50000000";
g
www.eeworm.com/read/278121/4147648
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_mac_out is
generic(
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : strin
www.eeworm.com/read/278121/4147654
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_lcell_comb is
generic(
lut_mask : integer := 65535;
sum_lutc_input : string := "datac";
lpm_type
www.eeworm.com/read/278121/4147666
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_out