代码搜索：Controller
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vhd controller.vhd
-- CONTROL UNIT OF THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;
entity cont_gen is
por
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vhd controller.vhd
-- CONTROL UNIT OF THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;
entity cont_gen is
por
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pin controller.pin
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
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qpf controller.qpf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
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sof controller.sof
www.eeworm.com/read/176838/9482639
vhd controller.vhd
-- CONTROL UNIT OF THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;
entity cont_gen is
por
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qws controller.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[P
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vhd controller.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CONTROLLER IS
PORT(CLK:IN STD_LOGIC;
RA,YA,GA,RB,YB,GB:OUT STD_LOGIC);
END CONTROLLER;
ARCHITECTURE ONE OF CONTROLLER IS
TYPE STATES IS(S0,S1,S
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