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Control System 的代码
traffic_control.rpt
Project Information d:\project\traffic_control.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/13/2006 08:37:57
Copyright (C) 1988-2000 Alt
control_interface.v
/******************************************************************************
*
* LOGIC CORE: Control Interface - Top level module
* MODULE NAME: control_interface()
* COMPANY
control2.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
entity control_main is
port (
a_small , sign_a , sign_b : in std_logic ;
control.o.d
control.o: control.c main.h C:/WinAVR/avr/include/avr/io.h \
C:/WinAVR/avr/include/avr/sfr_defs.h C:/WinAVR/avr/include/inttypes.h \
C:/WinAVR/avr/include/stdint.h C:/WinAVR/avr/include/avr/iom6
control_interface.v
/******************************************************************************
*
* LOGIC CORE: Control Interface - Top level module
* MODULE NAME: control_interface()
* COM
inv_control.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity inv_control is
generic (
stage : natural:=3);
port (
clk : in std_
tx_control.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
ram_control.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
entity ram_control is
generic (
Tx_nRX : natural := 0;
stage : natural := 3);
por
cfft_control.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
entity cfft_control is
generic (
Tx_nRx : natural := 0; -- tx = 1, rx = 0