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Control System 的代码
control.srs
#
#
#
# Created by Synplify VHDL Compiler version 7.0.0, Build 130R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sun Sep 01 1
control.jam
' Copyright (C) 1988-2001 Altera Corporation
' Any megafunction design, and related net list (encrypted or decrypted),
' support information, device programming or simulation file, and any other
'
control.tcl
project add_assignment "" "control" "" "" "EDA_DESIGN_ENTRY_SYNTHESIS_TOOL" "SYNPLIFY"
project add_assignment "" "eda_design_synthesis" "" "" EDA_INPUT_DATA_FORMAT EDIF
project add_assignment "" "ed