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Control System 的代码
control.tlg
Synthesizing work.control.body_control
Post processing for work.control.body_control
@W:"H:\can\cpld\rev_1\control.vhd":367:4:367:5|Optimizing register bit wr_a_up(0) to a constant 0
@W:"H:\can\cpl
control.plg
@P: Worst Slack : 475.100
@P: alea - Estimated Frequency : 54.9 MHz
@P: alea - Requested Frequency : 1.0 MHz
@P: alea - Estimated Period : 18.200
@P: alea - Requested Period : 1000.000
@P: