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control.qws

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 pt

control.hif

Version 6.0 Build 178 04/27/2006 SJ Full Version 2 21 OFF OFF OFF OFF OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- -- E

control.v

module control(en,D,DATA,cfm); input en; input[3:0] D; output cfm; output[23:0] DATA; reg[23:0] DATA; reg cfm; integer i=7; always @(negedge en) begin cfm=0; if(D[3:0]

control.qpf

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

control.done

Sun Feb 25 04:55:04 2007

control.pin

-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

control.v

module control(en,D,DATA,cfm,shift); input en; input[3:0] D; output cfm,shift; output[23:0] DATA; reg[23:0] DATA; reg cfm,shift; integer i; always @(negedge en) begin cfm=0; if(D[3:0]

control.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.mydefine.all; entity control is port(c_en:in std_logic; input:in std_logic_vector(7 downto 0); clk:in std_