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Control 的代码
sdram_control_4port.v
module Sdram_Control_4Port(
// HOST Side
REF_CLK,
RESET_N,
CLK,
CLK_18,
// FIFO Write Side 1
WR1_DATA,
WR1,
WR1_ADDR,
WR1_MAX_ADDR,
WR1_LENGTH,
WR
xmit_rcv_control_fsm.vhd
-- hds header_start
--
-- VHDL Architecture UART_TXT.xmit_rcv_control.symbol
--
-- Created:
-- by - user.group (host.domain)
-- at - 19:10:38 28 Aug 2001
--
-- Generated by M
gh_register_control_ce.vhd
-----------------------------------------------------------------------------
-- Filename: gh_register_control_ce.vhd
--
-- Description:
-- Control register with clock enable
-- mode = "00" wr
fuzzy_control_frame.java~1~
package fuzzy_control;
import java.awt.BorderLayout;
import java.awt.Dimension;
import javax.swing.JFrame;
import javax.swing.JPanel;
/**
* Title:
*
* Description:
*
fuzzy_control_frame.java~2~
package fuzzy_control;
import java.awt.BorderLayout;
import java.awt.Dimension;
import javax.swing.JFrame;
import javax.swing.JPanel;
import java.awt.*;
import javax.swing.ImageIcon;
publ
fuzzy_control_frame.java~3~
package fuzzy_control;
import java.awt.BorderLayout;
import java.awt.Dimension;
import javax.swing.JFrame;
import javax.swing.JPanel;
import java.awt.*;
import javax.swing.ImageIcon;
import j