代码搜索结果

log_puts {@N|Using encoding styles selected by FSM Explorer.} log_puts {Data created on Wed Nov 09 16:42:18 2005} define_attribute {work.data_control_fsm.verilog|i:cs[11:0]} syn_encoding {onehot

ngdbuild -ise "C:/training/desperf/labs/synthesis/synplify/verilog/synth_lab" -intstyle ise -dd _ngo -nt timestamp -i -p xc4vfx12-sf363-12 data_control.edn data_control.ngd ngdbuild -ise "C:/training

//_____________________________________________________________________________________ // This state machine creates the read enable for the channel FIFOs. It also creates the // output multiple

#Begin clock constraint define_clock -name {p:data_control|clk} -period 2.466 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.233 -route 0.000 #End clock constraint

log_puts {@N|Using encoding styles selected by FSM Explorer.} log_puts {Data created on Tue Nov 08 15:30:36 2005} define_attribute {work.data_control_fsm.rtl|i:cs[0:11]} syn_encoding {onehot}

ngdbuild -ise "C:/training/desperf/labs/synthesis/synplify/vhdl/synth_lab" -intstyle ise -dd _ngo -nt timestamp -i -p xc4vfx12-sf363-12 data_control.edn data_control.ngd ngdbuild -ise "C:/training/de

library ieee; use ieee.std_logic_1164.all; entity data_control_fsm is port ( clk : in std_logic; reset : in std_logic; next_ch : i

#Begin clock constraint define_clock -name {p:data_control|clk} -period 2.466 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.233 -route 0.000 #End clock constraint

ngdbuild -ise "C:/training/desperf/labs/synthesis/precision/verilog/synth_lab" -intstyle ise -dd _ngo -nt timestamp -uc data_control.ucf -p xc4vlx15-sf363-12 data_control.edf data_control.ngd map -is

//_____________________________________________________________________________________ // This state machine creates the read enable for the channel FIFOs. It also creates the // output multiple