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Flow report for ram_control Sat Jul 29 13:33:33 2006 Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Le

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

Flow Status : Successful - Sat Jul 29 13:33:18 2006 Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version Revision Name : ram_control Top-level Entity Name : ram_control Family : Cycl

EDA Netlist Writer report for ram_control Sat Jul 29 16:37:16 2006 Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; ----------------

Fitter report for ram_control Sat Jul 29 16:37:07 2006 Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1.

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

Flow Status : Successful - Sat Jul 29 16:37:07 2006 Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version Revision Name : ram_control Top-level Entity Name : ram_control Family : Cycl

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/ram_control.v source_file = 1

// Copyright (C) 1991-2005 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and