代码搜索：Control
找到约 10,000 项符合「Control」的源代码
代码结果 10,000
www.eeworm.com/read/418844/2082693
ucf data_control.ucf
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 2.5 ns HIGH 50 %;
www.eeworm.com/read/418844/2082695
sap data_control.sap
@ER
88NN0_0Fkb_k0l_kGH0M#;o
H_RPO4E_rjd:9N;
HOR3D FORm"hh; "
RNH3FODOC _8RoC"#sHC
";N3HR#O$M_#sCC"0RMC:s#"C0;b
oR
B;N3bRHO#_D FOR
4;N3bROODF hR"m"h ;b
NRD3OF_O CC8oRH"s#;C"
H
oROP_Er_jd9:
www.eeworm.com/read/418844/2082697
vhd data_control.vhd
library ieee;
use ieee.std_logic_1164.all;
entity data_control is
port (
clk : in std_logic;
reset : in std_logic;
rd_data_cha : in st
www.eeworm.com/read/418844/2082699
srr data_control.srr
#Build: Synplify Pro 8.8, Build 008R, Dec 7 2006
#install: Y:\XILI\Synplify_8_8\fpga_88
#OS: Windows 2000 5.0
#Hostname: SJC-XILISTG1
#Implementation: vhdl
#Fri Mar 16 10:05:14 2007
$ Sta
www.eeworm.com/read/418844/2082707
ucf data_control.ucf
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 2.5 ns HIGH 50 %;
www.eeworm.com/read/418844/2082708
v data_control.v
module data_control (input clk,
input reset,
input [3:0] pn_lock_rd_clk,
input [7:0] rd_data_cha,
input [7:0] rd_data_chb,
input [7:0] rd_data_chc,
www.eeworm.com/read/418844/2082710
sdc data_control.sdc
###################################################################################
# Mentor Graphics Corporation
#
#################################################################################
www.eeworm.com/read/418844/2082716
ucf data_control.ucf
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 2.5 ns HIGH 50 %;
www.eeworm.com/read/418844/2082718
sdc data_control.sdc
###################################################################################
# Mentor Graphics Corporation
#
#################################################################################
www.eeworm.com/read/418844/2082719
vhd data_control.vhd
library ieee;
use ieee.std_logic_1164.all;
entity data_control is
port (
clk : in std_logic;
reset : in std_logic;
rd_data_cha : in st