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Control 的代码
control.sat
define_design_name {control}
define_synthesis -family MAX7000
define_clock {|sysclk} -period 1000.000
define_clock {|iow} -period 1000.000
define_clock {|ior} -period 1000.000
define_clock {|wrb}
traffic control.plg
礦ision2 Build Log
Project:
E:\单片机\科研训练\TRFFIC-CONTROL\traffic control.uv2
Project File Date: 01/12/2008
Output:
control.jhd
MODULE control
control.vhd
library ieee;
use ieee.std_logic_1164.all;
entity control is
port(zuoduan,youduan:in std_logic;
over:out std_logic);
end control;
architecture one of control is
begin
ove
control.rpt
Project Information j:\20050820113\bahe1\control.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/25/2007 07:31:49
Copyright (C) 1988-2000 Alt
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(clk,start,stop,reset :in std_logic;
speed1,speed2,speed3 :in std_logic;
control.rpt
Project Information d:\mux\kechengsheji\control.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/12/2009 16:45:58
Copyright (C) 1988-2002 Al
control.c
/* control.c - control */
#include
#include
#include
#include
/*------------------------------------------------------------------------
* control -
control.cpp
#include
#include
using namespace std;
#include "control.h"
#include "body.h"
#include "world.h"
#include "connection.h"
#include "common.h"
control::control(world*w, body *b, co
control.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY control IS
PORT( mode: IN STD_LOGIC;
begend: IN STD_LOGIC; --k