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Control 的代码
control.tlg
Synthesizing work.control.body_control
Post processing for work.control.body_control
@W:"H:\can\cpld\rev_1\control.vhd":367:4:367:5|Optimizing register bit wr_a_up(0) to a constant 0
@W:"H:\can\cpl
control.sat
define_design_name {control}
define_synthesis -family MAX7000
define_clock {|sysclk} -period 1000.000
define_clock {|iow} -period 1000.000
define_clock {|ior} -period 1000.000
define_clock {|wrb}
control.srd
f "noname"; #file 0
f "c:\synplicity\synplify_70\lib\vhd\std.vhd"; #file 1
f "h:\can\cpld\rev_1\control.vhd"; #file 2
f "c:\synplicity\synplify_70\lib\vhd\std1164.vhd"; #file 3
f "c:\synplicity\sy
control.rpt
Project Information h:\can\cpld\rev_1\control.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 08/29/2013 15:13:46
Copyright (C) 1988-2001 Al
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.v
`timescale 1ns/10ps
module control(nGCLK, nWAIT,
nRESET, DABORT, IABORT, nFIQ, nIRQ,
ISYNC, CHSD, CHSE, ID, IA, irq_disable, fiq_disable,
flags_ex, load_pc_me, exception_to_id,
pc, inst_if,
control.v
module control(clk1,clk2,i,OE,reset);
parameter state_reset=9;
parameter state_spare=8;
input clk1,clk2;
output[2:0] i;
output OE;
output reset;
reg reset;
reg OE;
reg[2:0] i;
reg[3:0] state,next_stat
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.v
//name:control.v 主控模块 2006-5-1 version:1.0 作者：田世坤
//波形输出主控模块：
//输入：clk：系统时钟(10MHz);
// keysignal：按键信号;
//输出：DLedout：发光二极管，八位宽;
// ensqu:方波使能信号
// entri:三角波使能信号
// ensin
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_