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Control 的代码
control.tan.rpt
Timing Analyzer report for control
Sun Feb 25 04:50:01 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Noti
control.v
module control(en,D,DATA,cfm,shift);
input en;
input[3:0] D;
output cfm,shift;
output[23:0] DATA;
reg[23:0] DATA;
reg cfm,shift;
integer i;
always @(negedge en)
begin
cfm=0;
if(D[3:0]
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
control.vhd
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.edf
(edif control
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2007 11 23 13 41 36)
(author "Synplicity, Inc.")
(progra
control.tcl
project add_assignment "" "control" "" "" "EDA_DESIGN_ENTRY_SYNTHESIS_TOOL" "SYNPLIFY"
project add_assignment "" "eda_design_synthesis" "" "" EDA_INPUT_DATA_FORMAT EDIF
project add_assignment "" "ed