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Control 的代码
control.map.summary
Analysis & Synthesis Status : Successful - Wed Oct 10 21:54:37 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : control
Top-level Entity Name : control
Family : S
control.flow.rpt
Flow report for control
Wed Oct 10 21:54:59 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fl
control.asm.rpt
Assembler report for control
Wed Oct 10 21:54:56 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
control.map.rpt
Analysis & Synthesis report for control
Wed Oct 10 21:54:37 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal
control.hier_info
|control
clk => count[0].CLK
clk => count[1].CLK
clk1024 => bee~0.DATAB
clk1024 => clrc~reg0.CLK
clk1024 => setb~reg0.CLK
clk1024 => seta~reg0.CLK
clk500 => bee~3.DATAB
sa => seta~reg0.DATAIN
control.fit.summary
Fitter Status : Successful - Wed Oct 10 21:54:49 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : control
Top-level Entity Name : control
Family : Stratix
Device
control.tan.rpt
Timing Analyzer report for control
Wed Oct 10 21:54:59 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Noti
control.v
module control(EN_in,SW1,RST,Red1,Red2,Yellow1,Yellow2,Green1,Green2);
output Red1;
output Red2;
output Yellow1;
output Yellow2;
output Green1;
output Green2;
input [1:0] EN_in;//控制红黄绿灯切
control.v
module control(en,D,DATA,cfm,shift);
input en;
input[3:0] D;
output cfm,shift;
output[23:0] DATA;
reg[23:0] DATA;
reg cfm,shift;
integer i;
always @(negedge en)
begin
cfm=0;
if(D[3:0]