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Control 的代码
control.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
control.v
module control(en,D,DATA,cfm,shift);
input en;
input[3:0] D;
output cfm,shift;
output[23:0] DATA;
reg[23:0] DATA;
reg cfm,shift;
integer i;
always @(negedge en)
begin
cfm=0;
if(D[3:0]
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
control.vhd
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_