代码搜索：Comp

找到约 10,000 项符合「Comp」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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c test44x_ca03.c

//****************************************************************************** // MSP430-TEST44x Demo - Comp_A Used For Simple 2.2V Low Battery Detect // Description; Two comparator_A reference
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c test44x_ca03.c

//****************************************************************************** // MSP430-TEST44x Demo - Comp_A Used For Simple 2.2V Low Battery Detect // Description; Two comparator_A referenc
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www.eeworm.com/read/209559/4966653

c ppp_synctty.c

/* * PPP synchronous tty channel driver for Linux. * * This is a ppp channel driver that can be used with tty device drivers * that are frame oriented, such as synchronous HDLC devices. * * Comp
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www.eeworm.com/read/191025/5169771

java nulldeviceerrorhandler.java

package org.jconfig.error; /** * This class implements the so called NullDevice ErrorHandler. It just * swallows the error messages. This ErrorHandler is used as default to * be backward comp
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c ppp_synctty.c

/* * PPP synchronous tty channel driver for Linux. * * This is a ppp channel driver that can be used with tty device drivers * that are frame oriented, such as synchronous HDLC devices. * * Comp
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java paralist.java

package jaoso.framework.dao; /** * * Title: Jaoso * * * * Description: Jaoso Articles * * * * Copyright: Copyright (c) 2003 * * * * Comp
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www.eeworm.com/read/350097/3131534

c ppp_synctty.c

/* * PPP synchronous tty channel driver for Linux. * * This is a ppp channel driver that can be used with tty device drivers * that are frame oriented, such as synchronous HDLC devices. * * Comp
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www.eeworm.com/read/344017/3212762

pl init.pl

#!/usr/bin/perl # Purpose: Initialize the combinatorial tmp variables # to avoid instanciation in synthesis if ($#ARGV < 0) { die ("# Call: init.pl [getinit |infile
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sprj fdq.sprj

`timescale 1ns/1ns `include "fdq.vf" `include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
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prj prescale_counter.prj

`timescale 1ns/1ns `include "prescale_counter.v" `include "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
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